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Texas Instruments XIO2000A Translation Bridges

Texas Instruments XIO2000A PCI EXPRESS® to PCI® Bus Translation Bridges is fully compliant with the PCI Express to PCI/PCI-X Bridge Specification. The XIO2000A Bridge simultaneously supports up to eight posted and four non-posted transactions for each enabled virtual channel (VC) for downstream traffic. Up to six posted and four non-posted transactions are simultaneously supported for upstream traffic for each VC.

The TI XIO2000A Bridges support two independent VCs. The second VC is optimized for isochronous traffic types and quality-of-service (QoS) applications. Also, the bridge supports the advanced error reporting capability, including extended CRC (ECRC). Supplemental firmware or software is required to utilize both of these features thoroughly.

A robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are detected, then packet poisoning is supported for both upstream and downstream operations.

Features

  • Full x1 PCI Express throughput
  • Fully compliant with PCI Express to PCI/PCI-X bridge specification, revision 1.0
  • Fully compliant with PCI Express base specification, revision 1.0a
  • Fully compliant with PCI local bus specification, revision 2.3
  • Extended Virtual Channel (VC) support
  • Includes a second VC for quality-of-service and isochronous applications
  • PCI Express advanced error reporting capability, including ECRC support
  • Support for D1, D2, D3hot, and D3cold
  • Active state link power management saves power when packet activity on the PCI express link is idle, using both the L0s and L1 states
  • Wake event and beacon support
  • Error forwarding including PCI express
  • Data poisoning and PCI bus parity errors
  • Utilizes 100MHz differential PCI express common reference clock or 125MHz single-ended reference clock
  • Robust pipeline architecture to minimize transaction latency
  • Full PCI local bus 66MHz/32-Bit throughput
  • Support for six subordinate PCI bus masters with the internal configurable, 2-level prioritization scheme
  • Low power design (<350mW) ensures ease of implementation
  • XIO2000AI Supports industrial temperatures at 33MHz bus speeds
  • Two package options of 15mm x 15mm and 12mm x 12mm
  • Internal PCI arbiter supporting up to 6 external PCI masters
  • Advanced VC arbitration options include VC1 strict priority, hardware-fixed round-robin, and 32-phase, weighted round-robin
  • Advanced PCI bus port arbitration options include 128-phase, weighted round-robin time-based and 128-phase, weighted round-robin aggressive time-based
  • Advanced PCI isochronous windows for memory space mapping to a specified traffic class
  • Advanced PCI Express message signaled interrupt generation for serial IRQ interrupts from cardbus applications
  • External PCI bus arbiter option
  • PCI Bus LOCK support
  • Clock run and power override support
  • Six buffered PCI clock outputs (33MHz or 66MHz)
  • PCI bus interface 3.3V and 5.0V (33MHz only at 5.0V) tolerance options
  • Integrated AUX power switch drains VAUX
  • Power only when main power is off
  • Eight 3.3V, multifunction, general-purpose I/O terminals
  • Memory-mapped EEPROM serial-bus controller supporting PCI express power budget/limit extensions for add-in cards
  • Compact footprint, 201-Ball, GZZ MicroStar™ BGA (XIO2000A only), lead-free 201-Ball, ZZZ MicroStar BGA; 175-Ball ZHC MicroStar BGA; or 175-Ball ZHH MicroStar BGA

Additional Resources

Published: 2021-02-04 | Updated: 2024-05-22