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Texas Instruments LMK5C33216 Ultra-Low Jitter Clock Synchronizer

Texas Instruments LMK5C33216 Ultra-Low Jitter Clock Synchronizer is a high-performance network clock generator, synchronizer, and jitter attenuator. It comes with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications. The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independently of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains. The Texas Instruments LMK5C33216 is fully programmable through an I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.

Features

  • BAW APLL with 40fs RMS jitter at 491.52MHz
  • Three high-performance digital-phase locked loops (DPLLs) with a paired analog-phase locked loops (APLLs)
    • Programmable DPLL loop bandwidth from 0.01Hz to 4kHz
    • -116dBc/Hz at 100Hz offset at 122.88MHz DPLL TDC noise with ≥ 20MHz TDC rate
  • Two differential or single-ended DPLL inputs
    • 1Hz to 800MHz differential
    • Hitless switching with phase cancellation and/or phase slew control
    • Priority-based reference selection
  • 16 outputs with a programmable format
    • 1000MHz LVPECL/LVDS/HSDS
    • 3000MHz CML on OUT4 and OUT6
    • 200MHz LVCMOS on OUT0 and OUT1
  • Single 3.3V supply with internal LDOs
  • I2C or 3-wire/4-wire SPI interface
  • Requires single XO/TCXO/OCXO
  • 40-bit DPLL or APLL DCO, < 1ppt
  • Holdover with phase build-out upon exit
  • Zero delay mode with programmable delay
  • User-programmable EEPROM
  • Supports 105°C PCB temperature

Applications

  • 4G and 5G wireless networks
  • Base Band Unit (BBU)
  • Active Antenna Unit (AAU)
  • Remote Radio Unit (RRU)
  • Network Switch (5G HUB)
  • Small cell

Functional Block Diagram

Block Diagram - Texas Instruments LMK5C33216 Ultra-Low Jitter Clock Synchronizer
Published: 2021-02-10 | Updated: 2022-03-11