DDR2 SDRAM

ISSI DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ISSI DDR2 SDRAM has on-die termination (ODT) and programmable burst lengths of 4 or 8. The on-chip DLL aligns DQ and DQs transitions with CK transitions. 

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Description Datasheet Availability Pricing (GBP) Filter the results in the table by unit price based on your quantity.
Qty. RoHS ECAD Model Type
Memory Size
Data Bus Width
Maximum Clock Frequency
Package/Case
Organisation
Access Time
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Series
Packaging
ISSI DRAM 512M, 1.8V, 333Mhz 32M x 16 DDR2
Datasheet
Non-Stocked Lead-Time 10 Weeks
Min.: 1
Mult.: 1

SDRAM - DDR2 512 Mbit 16 bit 333 MHz BGA-84 32 M x 16 450 ps 1.7 V 1.9 V 0 C + 85 C IS43DR16320D Tray
ISSI DRAM 1G, 1.8V, DDR2, 128Mx8, 333Mhz at CL5, 60 ball BGA, (8mmx 10.5mm), RoHS
Datasheet
Non-Stocked Lead-Time 10 Weeks
Min.: 242
Mult.: 242

SDRAM - DDR2 1 Gbit 8 bit 333 MHz BGA-60 128 M x 8 450 ps 1.7 V 1.9 V 0 C + 70 C IS43DR81280B Tray
ISSI DRAM 512M, 1.8V, 333Mhz 64Mx8 DDR2 SDRAM
Datasheet
Non-Stocked Lead-Time 10 Weeks
Min.: 242
Mult.: 242

SDRAM - DDR2 512 Mbit 8 bit 333 MHz BGA-60 64 M x 8 450 ps 1.7 V 1.9 V - 40 C + 85 C IS43DR86400C Tray