ADC3244EIRGZT

Texas Instruments
595-ADC3244EIRGZT
ADC3244EIRGZT

Mfr.:

Description:
Analog to Digital Converters - ADC Dual-channel 14-bit 125-MSPS analog-to-d

ECAD Model:
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Availability

Stock:
Non-Stocked
Factory Lead Time:
18 Weeks Estimated factory production time.
Minimum: 250   Multiples: 250
Unit Price:
£-.--
Ext. Price:
£-.--
Est. Tariff:
This Product Ships FREE

Pricing (GBP)

Qty. Unit Price
Ext. Price
Full Reel (Order in multiples of 250)
£85.68 £21,420.00
2,500 Quote

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Analog to Digital Converters - ADC
RoHS:  
ADC3244E
SMD/SMT
VQFN-48
14 bit
2 Channel
Serial LVDS
125 MS/s
Differential
Pipeline
1.8 V
1.8 V
71.6 dB
- 50 C
+ 105 C
Reel
Brand: Texas Instruments
ENOB - Effective Number of Bits: 11.8 Bit
Features: Low Power
Moisture Sensitive: Yes
Number of Converters: 2 Converter
Pd - Power Dissipation: 325 mW
Product: Analog to Digital Converters
Product Type: ADCs - Analog to Digital Converters
Reference Type: External, Internal
SFDR - Spurious Free Dynamic Range: 93 dB
SINAD - Signal to Noise and Distortion Ratio: 71.1 dB
Factory Pack Quantity: 250
Subcategory: Data Converter ICs
THD - Total Harmonic Distortion: 80 dBc
Type: Low Power
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CAHTS:
8542390000
USHTS:
8542390030
MXHTS:
8542399999
ECCN:
3A991.c.3

ADC3244E 14-bit Analog-to-Digital Converters

Texas Instruments ADC3244E 14-bit Analog-to-Digital Converters offer high-linearity, ultra-low power, dual-channel, 14-bit, and a 25MSPS to 125MSPS range. The ADC3244E is designed specifically to support demanding, high-input frequency signals with large dynamic range requirements. The Texas Instruments ADC3244E supports serial, low-voltage differential signaling (LVDS), reducing the number of interface lines and permitting high system integration density. The data from each ADC are serialized and output over two LVDS pairs. The device implements an internal phase-locked loop (PLL) that multiplies the incoming ADC sampling clock to gather the bit clock used to serialize the 14-bit output data from each channel. The frame, bit clocks, and serial data streams are transmitted as LVDS outputs. The device provides an input clock divider, allowing system clock architecture design more flexibility. Additionally, the SYSREF input enables complete system synchronization.